1. Field of the Invention
The present invention relates to a test apparatus that tests a semiconductor device such as memory or the like.
2. Description of the Related Art
Memory such as DRAM has a problem in that defective memory cells occur with a certain probability. In a case in which, when a part of memory cells are defective, judgment is made that the memory itself is defective, this leads to marked reduction in yield. In order to solve such a problem, such memory is provided with a redundancy circuit that can be used as a backup for such defective cells. A test apparatus tests memory so as to generate a quality judgment result (fail information) with respect to the memory cell arrays, and stores the quality judgment result thus generated in fail memory. The test apparatus acquires a redundancy repair state based on the fail information. Subsequently, laser repair is performed according to the redundancy repair state thus acquired.
FIG. 1 is a block diagram showing a test system including a test apparatus 500 investigated by the present inventors. The test system 600 includes the test apparatus 500 that tests a DUT 602, an EWS (Engineering Workstation) 604, and a network hub 606.
The EWS 604 executes a test program so as to integrally control the overall operation of the test apparatus 500. The EWS 604 acquires and stores various kinds of data such as test results and the like. The EWS 604 is connected to the test apparatus 500 via the hub 606 and a high speed bus such as gigabit Ethernet (trademark) or the like.
The test apparatus 500 tests multiple DUTs (devices under test) 602 at the same time in a parallel manner. Furthermore, the test apparatus 500 performs pass/fail judgment, and performs calculation so as to acquire a redundancy repair state. The test apparatus 500 includes multiple CPU (Central Processing Unit) boards 510 and multiple PE (Pin Electronics) boards 520.
Each PE board 520 is configured to be capable of measuring multiple (e.g., twelve) DUTs 602. Each PE board 520 mounts multiple PE circuits 522, multiple fail memory 524, an MRA interface 526, and a test processor 528. The test processor 528 controls the PE circuits 522 mounted on the same PE board 520. Each PE circuit 522 is assigned to multiple DUTs 602. Each PE circuit 522 generates a test pattern according to the control operation of the test processor 528, and supplies the test pattern thus generated to the DUTs 602. Data that corresponds to the test pattern is written to the DUT 602 configured as memory. Each PE circuit 522 reads out the data written to the corresponding DUT 602, compares the data thus read out with expected value data, and acquires fail information that represents the comparison result. Each PE circuit 522 includes a timing generator, a pattern generator, a waveform shaper, a pattern comparator, and the like, for example. Each PE circuit 522 may be configured as a function LSI integrated on a single semiconductor chip. The fail information generated by each PE circuit 522 is written to the corresponding fail memory 524. Each fail memory 524 includes FAM (Fail Address Map) or FMB (Fail Bit Map).
Each CPU board 510 is configured such that it can be connected to multiple (up to a maximum of eight, for example) PE boards 520. Each CPU board 510 is connected to the PE boards 520 via a high-speed interface having a multi-gigabit data transmission rate. Each CPU board 510 includes multiple RCPUs (Repair CPUs) 512 and a test processor 514.
The CPU board 510 and the PE board 520 are connected to each other via a bus 530 and a pair of transceivers 540A and 540B. The test processor 514 included in the CPU board 510 is connected to the respective test processors 528 of the multiple PE boards 520 via a bus 532. The bus 532 is configured to have a bandwidth on the order of 1 Gbps. Each PE board 520 is controlled via the bus 530 in a real-time manner.
Each RCPU 512 is assigned to multiple (e.g., two) PE boards 520. For example, the first RCPU 512_1 is assigned to the two PE boards 520_1 and 520_2 such that it is assigned to six fail memory 524 mounted on the PE boards 520_1 and 520_2. Each RCPU 512 controls the corresponding six fail memory 524 in a real-time manner. Furthermore, the RCPU 512 receives the fail information from each fail memory 524, and calculates a repair state. The second RCPU 512_2 is assigned to six fail memory 524 mounted on a different pair of PE boards 520. The same can be said of the other RCPUs 512. Specifically, the RCPU 512_1 and the MRA interface 526 are connected to each other via the transceivers 540A and 540B and the bus 534.
Each MRA interface 526 monitors multiple (e.g., three) fail memory 524. When a flag is asserted, which indicates that acquisition of fail information has been completed for a prescribed unit (e.g., for one of the DUTs), the MRA interface 526 transfers the fail information to the corresponding RCPU 512 via the bus 532. The bus 532 is assigned to each fail memory, and is configured to have a bandwidth on the order of 1 Gbps for each fail memory. The RCPU 512 performs Redundancy Analysis calculation (which is also referred to as “RA processing”) for calculating a repair state based on the fail information transmitted from the MRA interface 526.
With the test apparatus 500 having such an architecture shown in FIG. 1, each RCPU 512 performs both the control operation (which will also be referred to as the “FM control operation”) for each fail memory 524 and the RA processing. The FM control operation must be performed in a real-time manner. That is to say, the RCPU 512 is required to provide a high-speed FM control operation. In contrast, the RA processing requires a long calculation time. With conventional techniques, there is a need to develop such a CPU board 510 so as to satisfy the specifications for both the RA processing and the FM control operation. Furthermore, there is a need to design an interface between the CPU board 510 and the PE board 520 so as to satisfy the requisite performance. With such an example shown in FIG. 1, the data transmission for the test processor side requires a total of 8 Gbps, and the data transmission for the RCPUs 512 side requires a total of 6 Gbps.
As a result obtained by investigating the test apparatus 500 shown in FIG. 1, the present inventor has come to recognize the following problem.
The amount of calculation to be provided by each RCPU changes according to the number of DUTs 602 to be processed. Accordingly, there is a need to design the RCPU 512 to have a calculation processing capacity such that the RA processing can be completed within a realistic period of time even in a case in which the RCPU 512 has the greatest load concentration (i.e., in a case in which the number of DUTs is large). This can lead to increased costs for such a CPU. In addition, the RCPU 512 thus designed has an obviously unnecessarily high calculation processing capacity in a case in which the RCPU 512 operates in a light load state (in a case in which the number of DUTs is small).
Furthermore, the interface between the CPU board 510 and the PE board 520 is required to have a bandwidth of several Gbps. Thus, there is a need to employ the transceivers 540A and 540B and the bus 530 designed as a dedicated interface so as to satisfy the specifications. However, improvement occurs in the performance of DUTs every two to three years. This involves an increase in the amount of fail information data. Accordingly, this requires a great design change of the interface between the CPU board 510 and the PE board 520. This often leads to a problem of an increased development period and a problem of increased costs.
The CPUs that can be employed in the development of a new-generation test apparatus are not always configured to have the same architectures as those of CPUs employed in a previous-generation test apparatus. In some cases, the new-generation CPUs have poor compatibility. In this case, evaluation of CPU compatibility requires enormous effort.
If the development of the CPU board 510 takes a long period of time, this leads to a long time lag between the design start time point and the product release time point. Typically, the circuit elements such as CPUs are selected based on the design specifications defined at the design start time point. Accordingly, the CPUs thus selected at the design start time point will become one generation behind at the product release time. Thus, such CPUs can become a bottleneck.
In recent years, as semiconductor devices are improved to have an increased operating speed and an increased capacity, an amount of data to be processed by the test apparatus 500 has been steadily increasing. Accordingly, in a case in which the test apparatus 500 having a conventional architecture is configured to support a semiconductor device configured according to a leading-edge technique, such an arrangement leads to a problem of very high costs.